We are going to design and simulate low power fractional-N phase-locked loop (FNPLL) frequency synthesizer for industrial\napplication, which is based on VLSI. The design of FNPLL has been optimized using different VLSI techniques to acquire\nsignificant performance in terms of speed with relatively less power consumption. One of the major contributions in optimization\nis contributed by the loop filter as it limits the switching time between cycles. Sigma-delta modulator attenuates the noise generated\nby the loop filter. This paper presents the implementation details and simulation results of all the blocks of optimized design.
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